Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in nonvolatile memory. In some CPLDs, configuration data is stored on-chip in nonvolatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in nonvolatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Some FPGAs, such as the Virtex™ FPGA family, available from Xilinx, Inc. of San Jose, Calif., can be programmed to incorporate blocks with pre-designed functionalities, i.e., “cores.” A core can include a predetermined set of configuration bits that program the FPGA to perform one or more functions. Alternatively, a core can include source code or schematics that describe the logic and connectivity of a design. Typical cores can provide, but are not limited to, digital signal processing (DSP) functions, memories, storage elements, and math functions. Some cores include an optimally floorplanned layout targeted to a specific family of FPGAs. Cores can also be parameterizable, i.e., allowing the user to enter parameters to activate or change certain core functionality.
Conventionally, cores have been targeted to a lowest common denominator for deployment across FPGAs of a family. This in part has been due to not knowing where in the FPGA programmable circuitry (“FPGA fabric”) a user may instantiate a core. Additionally, one or more cores may be part of an overall user design, and thus integration and verification of such overall design includes each core used therein. Furthermore, because one or more cores may be part of the overall user design, each of such cores may be recompiled each time a user's design is changed. This recompilation may lead to variation in behavior, which may lead to issues with design convergence.
To avoid complexity associated with system level designs involving instantiation of a user design including one or more cores in FPGA fabric, Application Specific Standard Products (ASSPs) have been used with FPGAs. Basically, the ASSP takes the place of the core in the user design. Use of an ASSP may save time with respect to system integration and verification issues, as customer off-the-shelf (COTS) ASSPs having known functional and timing compliance may be “black boxed.”
However, use of ASSPs means having to use a widely accepted design protocol, as ASSPs conventionally are not made for an industry known design protocol if such is not widely accepted. Furthermore, ASSPs may not support optional features of such widely accepted protocols. Lastly, use of an ASSP means that the ASSP has to be interfaced with other ICs on a circuit board including the FPGA, and use of such ASSP takes up circuit board space and thermal budget.
Still others have incorporated FPGA hardware into an Application Specific Integrated Circuit (ASIC). However, such an FPGA-ASIC hybrid has conventionally been too costly in some applications due to developmental costs of the FPGA-ASIC hybrid. Additionally, FPGA-ASIC hybrids may have too long a time-to-market delay when compared with using COTS ASSPs and FPGAs in combination.
Lastly, a Programmable System-on-Chip (PSOC) may be used. A PSOC is an ASSP with fixed functionality integration of one or more interfaces together with a programmable fabric region. However, such fixed function interfaces limit application of PSoCs.